3886A Datasheet | National Semiconductor

Description The DS3886A is a higher speed, lower power, pin patible version of the DS3886. The DS3886A is one in a series of transceivers designed specifically for the implementation of high performance Futurebus+ and proprietary bus interfaces. The DS3886A is a BTL 9-Bit Latching Data Transceiver designed to conform to IEEE 1194.1 (Backplane Transceiver Logic - BTL) as specified in the IEEE 896.2 Futurebus+ specification. The DS3886A incorporates an edge-triggered latch in the driver path which can be bypassed during fall-through mode of operation and a transparent latch in the receiver path. Utilization of the DS3886A simplifies the implementation of byte wide address/data with parity lines and also may be used for the Futurebus+ status, tag and mand lines. The DS3886A driver output configuration is an NPN open collector which allows Wired-OR connection on the bus. Each driver output incorporates a Schottky diode in series with it’s collector to isolate the transistor output capacitance from the bus, thus reducing the bus loading in the inactive state. The bined output capacitance of the driver output and receiver input is less than 5 p F. The driver also has high sink current capability to ply with the bus loading requirements defined within IEEE 1194.1 BTL specification. Backplane Transceiver Logic (BTL) is a signaling standard that was invented and first introduced by National Semiconductor, then developed by the IEEE to enhance the performance of backplane buses. BTL patible transceivers feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum noise immunity. The BTL standard eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends. The...