54173 Datasheet PDF

National Semiconductor 54173

The high-impedance state and increased high-logic-level drive provide these flip-flops with the capability of driving the bus lines in a bus-organized system without need for interface or pull-up components Gated enable inputs are provided for controlling the entry of data into the flip-flops When both data-enable inputs are low data at the D inputs are loaded into their respective flipflops on the next positive transition of the buffered clock input Gate output control inputs are also provided When both are low the normal logic states of the four outputs are available for driving the loads...