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5497 - Synchronous Modulo-64 Bit Rate Multiplier

General Description

The ’97 contains a synchronous 6-stage binary counter and six decoding gates that serve to gate the clock through to the output at a sub-multiple of the input frequency The output pulse rate relative to the clock frequency is determined by signals applied to the Select (S0 S5) inputs Both tr

Key Features

  • 010101 0101 5.

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Full PDF Text Transcription (Reference)

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5497 DM7497 Synchronous Modulo-64 Bit Rate Multiplier June 1989 5497 DM7497 Synchronous Modulo-64 Bit Rate Multiplier General Description The ’97 contains a synchronous 6-stage binary counter and six decoding gates that serve to gate the clock through to the output at a sub-multiple of the input frequency The output pulse rate relative to the clock frequency is determined by signals applied to the Select (S0–S5) inputs Both true and complement outputs are available along with an enable input for each A Count Enable input and a Terminal Count output are provided for cascading two or more packages An asynchronous Master Reset input prevents counting and resets the counter Connection Diagram Dual-In-Line Package Logic Symbol TL F 9780 – 2 TL F 9780 – 1 VCC e Pin 16 GND e Pin 8 Order Nu