54AC161 Datasheet | National Semiconductor

.. - 54ACT161 Synchronous Presettable Binary Counter November 1998 - 54ACT161 Synchronous Presettable Binary Counter General Description The ’AC/’ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The ’AC/ ’ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. n n n n n n Synchronous counting and loading High-speed synchronous expansion Typical count rate of 125 MHz Outputs source/sink 24 m A ’ACT161 has TTL-patible inputs Standard Microcircuit Drawing (SMD) - ’AC161: 5962-89561 - ’ACT161: 5962-91722 Features n ICC reduced by 50% Logic Symbols Pin Names CEP CET CP MR P0- P3 PE Q0- Q3 TC DS100274-1 Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output IEEE/IEC DS100274-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100274 .national. Connection Diagrams Pin Assignment for DIP and Flatpak The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. DS100274-3 Pin Assignment for LCC Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock...