GENERAL DESCRIPTION
Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). n n n n n n Multiplexed real-time and stored data transfers TRI-STATE outputs 300 mil slim dual-in-line package Outputs source/sink 24 mA ’ACT646 has TTL compatible inputs Standard Microcircuit Drawing (SMD) — ’AC646: 5962-89682 FEATURES
n Independent registers for A and B buses Logic Symbols Pin Names A0–A7 B0–B7 CPAB, CPBA SAB, SBA G DS100231-1 DESCRIPTION
Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input DIR IEEE/IEC DS100231-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100231 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100231-3 DS100231-4 Real Time Transfer A-Bus to B-Bus Storage from Bus to Register DS100231-9 DS100231-7 FIGURE 1.
National Semiconductor
