GENERAL DESCRIPTION
Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH FEATURES
n n n n ICC reduced by 50% Output source/sink 24 mA ’ACT74 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC74: 5962-88520 — ’ACT74: 5962-87525 Logic Symbols DS100266-2 DS100266-1 Pin Names IEEE/IEC D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 DESCRIPTION
Data Inputs Clock Pulse Inputs Direct Clear In...
National Semiconductor
