GENERAL DESCRIPTION
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. n Ideal for addressable register applications n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n Outputs source/sink 24 mA n See ’273 for master reset version n See ’373 for transparent latch version n See ’374 for TRI-STATE ® version n ’ACT377 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) — ’AC377: 5962-88702 — ’ACT377: 5962-87697 FEATURES
n ICC reduced by 50% Logic Symbols IEEE/IEC DS100290-1 DS100290-2 Pin Names D0–D7 CE Q0–Q7 CP DESCRIPTION
Data Inputs Clock Enable (Active LOW) Data Outputs Clock Pulse Input TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
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