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54F 74F273 Octal D Flip-Flop
Obsolete
May 1995
54F 74F273 Octal D Flip-Flop
General Description
The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously
The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements
Features
Y Ideal buffer for MOS microprocessor or memory Y Eight edg
54F273 Datasheet
