54F280 Overview
The ’F280 is a high-speed parity generator checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH If an even number of inputs is HIGH the Sum Even output is HIGH If an odd number is HIGH the Sum Even output is LOW The Sum Odd output is the plement of the Sum Even output.
54F280 Key Features
- I8 RO RE
- 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to est
