54F676 Overview
The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output When the Mode (M) input is HIGH information present on the parallel data (P0 P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal When M is LOW data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant...
54F676 Key Features
- 3 RRD-B30M105 Printed in U S A
- P15 CS CP M SI SO
- P15 are entered into the register on the falling edge of CP The SO output represents the Q15 register output To prevent