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54HC148 - 8-3 Line Priority Encoder

General Description

This priority encoder utilizes advanced silicon-gate CMOS technology It has the high noise immunity and low power consumption typical of CMOS circuits as well as the speeds and output drive similar to LB-TTL This priority encoder accepts 8 input request lines 0 7 and outputs 3 lines A0

Key Features

  • Y Typical propagation delay 13 ns Y Wide supply voltage range 2V.
  • 6V Connection Diagram Dual-In-Line Package Truth Table Order Number MM54HC148 or MM74HC148 TL F 9390.
  • 1 Inputs Outputs EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MM54HC148 MM74HC148 8-3 Line Priority Encoder February 1988 MM54HC148 MM74HC148 8-3 Line Priority Encoder General Description This priority encoder utilizes advanced silicon-gate CMOS technology It has the high noise immunity and low power consumption typical of CMOS circuits as well as the speeds and output drive similar to LB-TTL This priority encoder accepts 8 input request lines 0– 7 and outputs 3 lines A0–A2 The priority encoding ensures that only the highest order data line is encoded Cascading circuitry (enable input EI and enable output EO) has been provided to allow octal expansion without the need for external circuitry All data inputs and outputs are active at the low logic level All inputs are protected from damage due to static discharge by internal diode clamps to VCC and