54LS114 Datasheet | National Semiconductor

54LS114 Dual JK Negative Edge-Triggered Flip-Flop with mon Clocks and Clears June 1989 54LS114 Dual JK Negative Edge-Triggered Flip-Flop with mon Clocks and Clears General Description The ’LS114 Features individual J K and set inputs and mon clock and mon clear inputs When the clock goes HIGH the inputs are enabled and data will be accepted The logic level of the J and K inputs may be allowed to change when the Clock Pulse is HIGH and the bistable will perform according to the truth table as long as the minimum setup times are observed Input data is transferred to the outputs on the negative-going edge of the clock pulse Connection Diagram Dual-In-Line Package Logic...