54LS42
Overview
These BCD-to-decimal decoders consist of eight inverters and ten four-input NAND gates The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates Full decoding of input logic ensures that all outputs remain off for all invalid (10-15) input conditions Connection Diagram Dual-In-Line Package TL F 6365 - 1 Order Number 54LS42DMQB 54LS42FMQB DM54LS42J DM54LS42W DM74LS42M or DM74LS42N See NS Package Number J16A M16A N16E or W16A Logic Diagram.
