ADC12QS065
Description
This is Preliminary Information for a product currently in development. ALL specifications are design targets and are subject to change.
Key Features
- n n n n n n
- Single +3.0V supply operation Internal sample-and-hold Internal reference Low power consumption Power down mode Clock and Data Frame Timing 780 Mbps serial LVDS data rate (at 65 MHz clock) LVDS serial output rated for 100 Ohm load Key Specifications n n n n n n n
- Resolution DNL SNR (fIN = 10 MHz) SFDR (fIN = 10 MHz) ENOB (at Nyquist) Power Consumption -- Operating, 65 MSPS, per ADC -- Power Down Mode 12 Bits ± 0.3 LSB (typ)
- 5 dB (typ) 85 dB (typ) 11 Bits (typ) 200 mW (typ) < 3 mW (typ)
