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~National
~ Semiconductor
PRELIMINARY eecnn;)
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CGS64/74C800/801/802, CGS64/74CT800/801/802,
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CGS/74LCT800/801/802
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Low Skew PLL 1-to-8 CMOS Clock Driver
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General Description
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These minimum skew clock drivers are designed for Clock Generation and Support (CGS) applications operating at high frequencies utilizing a phase lock loop. The phase lock loop allows for outputs to lock-on to either SyncLO or SyncL1 inputs, which could be operating at different frequencies. This product is ideal for applications requiring clock synchronization and distribution of either on or off board components.