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CLC016 Datasheet Data Retiming Pll With Automatic Rate Selection

Manufacturer: National Semiconductor (now Texas Instruments)

Overview: CLC016 Data Retiming PLL with Automatic Rate Selection July 1998 CLC016 Data Retiming PLL with Automatic Rate.

General Description

National’s linear CLC016 is a low-cost, monolithic, data retiming phase-locked loop (PLL) designed for high-speed serial clock and data recovery.

The CLC016 simplifies highspeed data recovery in multi-rate systems by incorporating auto-rate select (ARS) circuitry on chip.

This function allows the user to configure the CLC016 to recognize up to four different data rates and automatically adjust to provide accurate, low-jitter clock and data recovery.

Key Features

  • n n n n n n n n n n n Retimed data output Recovered clock output Auto and manual rate select modes Four user-configurable data rates No potentiometers required External loop bandwidth control Frequency detector for lock acquisition Carrier detect output Output MUTE function Single supply operation: +5V or.
  • 5.2V Low cost Key Specifications n Low jitter: 130 pspp @ 270 Mbps, 0.25% fractional loop bandwidth (0.675 MHz) n High data rates: 40 Mbps.
  • 400 Mbps n Low supply current: 100.

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CLC016 Distributor