This page provides the datasheet information for the COP888CL, a member of the COP888CL-XXX_N 8-Bit Microcontroller family.
Datasheet Summary
Description
The COP888 family of microcontrollers uses an 8-bit single chip core architecture fabricated with National Semiconductor’s M2CMOSTM process technology The COP888CL is a member of this expandable 8-bit core processor family of microcontrollers (Continued)
Y
Packages 44 PLCC with 40 I O pins 40 DIP w
Features
Y
Y Y
Two 16-bit timers each with two 16-bit registers supporting Processor Independent PWM mode External Event counter mode Input Capture mode 4 kbytes of on-chip ROM 128 bytes of on-chip RAM
Y Y Y
Additional Peripheral Features
Y Y Y Y
Idle Timer Multi-input Wake Up (MIWU) with optional interrupts (8).
COP888CF- 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and A/D Converter
COP888CG- 8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory/ Comparators and USART
COP888CS- 8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory/ Comparators and USART
COP888EB- 8-Bit CMOS ROM Based Microcontrollers with 8k Memory/ CAN Interface/ 8-Bit A/D/ and USART
COP888EG- 8-Bit CMOS ROM Based Microcontrollers with 4k to 24k Memory/ Comparators and USART
COP888EK- 8-Bit CMOS ROM Based Microcontrollers with 8k Memory/ Comparator/ and Single-slope A/D Capability
COP888FH- 8-Bit CMOS ROM Based Microcontrollers with 12k Memory/ Comparators/ USART and Hardware Multiply/Divide
COP888GD- 8-Bit CMOS ROM Based Microcontrollers with 16k
Full PDF Text Transcription
Click to expand full text
COP688CL COP684CL COP888CL COP884CL COP988CL COP984CL 8-Bit Microcontroller
September 1996
COP688CL COP684CL COP888CL COP884CL COP988CL COP984CL 8-Bit Microcontroller
General Description
The COP888 family of microcontrollers uses an 8-bit single chip core architecture fabricated with National Semiconductor’s M2CMOSTM process technology The COP888CL is a member of this expandable 8-bit core processor family of microcontrollers (Continued)
Y
Packages 44 PLCC with 40 I O pins 40 DIP with 36 I O pins 28 DIP with 24 I O pins 28 SO with 24 I O pins
CPU Instruction Set Feature
Y Y
Key Features
Y
Y Y
Two 16-bit timers each with two 16-bit registers supporting Processor Independent PWM mode External Event counter mode Input Capture mode 4 kbytes of on-chip ROM 128 bytes of on-chip RAM
Y Y Y