This device contains three independent gates each of which performs the logic NAND function
Connection Diagram
Dual-In-Line Package
TL F 6619
1
Order Number DM54L10J or DM54L10W See NS Package Number J14A or W14B
Function Table
Y e ABC Inputs A X X L H B X L X H C L X X H Output Y H H
Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
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DM54L10 Triple 3-Input NAND Gates
June 1989
DM54L10 Triple 3-Input NAND Gates
General Description
This device contains three independent gates each of which performs the logic NAND function
Connection Diagram
Dual-In-Line Package
TL F 6619 – 1
Order Number DM54L10J or DM54L10W See NS Package Number J14A or W14B
Function Table
Y e ABC Inputs A X X L H B X L X H C L X X H Output Y H H H L
H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level
C1995 National Semiconductor Corporation
TL F 6619
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Note)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 8V Input Voltage 5 5V Operating Free Ai
DM54L10 Datasheet
