Datasheet4U Logo Datasheet4U.com

DM54L73 - Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

Description

This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops after a complete clock pulse While the clock is low the slave is isolated from the master On the positive transition of the clock the data from the

📥 Download Datasheet

Datasheet preview – DM54L73

Datasheet Details

Part number DM54L73
Manufacturer National Semiconductor
File Size 88.21 KB
Description Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
Datasheet download datasheet DM54L73 Datasheet
Additional preview pages of the DM54L73 datasheet.

📁 Similar Datasheet

  • DM54L89A - 64-BIT READ/WRITE MEMORIES (ETC)
  • DM54LS47 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS48 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS49 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54141 - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM54155 - Dual 2-Line to 4-Line Decoders/Demultiplexers (ETC)
  • DM5441A - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM5446A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5447A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5448 - BCD/7-Segment Decoder/Driver (MSI)
Other Datasheets by National Semiconductor
  • DM54L74 - Dual Positive Edge Triggered D Flip-Flop
  • DM54L00 - Quad 2-Input NAND Gates
  • DM54L00 - Quad 2-Input NAND Gates
  • DM54L02 - Quad 2-Input NOR Gates
  • DM54L04 - Hex Inverting Gate
  • DM54L10 - Triple 3-Input NAND Gates
  • DM54L93 - Decade/ Divide-by-12/ and Binary Counters
  • DM54L95 - 4-Bit Parallel Access Shift Registers

Full PDF Text Transcription

Click to expand full text
DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1989 DM54L73 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops after a complete clock pulse While the clock is low the slave is isolated from the master On the positive transition of the clock the data from the J and K inputs is transferred to the master While the clock is high the data from the J and K inputs are disabled On the negative transition of the clock the data from the master is transferred to the slave The logic states of the J and K inputs must not be allowed to change while the clock is high Data is tr
Published: |