Datasheet4U Logo Datasheet4U.com

DM54LS165 - 8-Bit Parallel In/Serial Output Shift Registers

Description

This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked Parallel-in access is made available by eight individual direct data inputs which are enabled by a low level at the shift load input These registers also feature gated clock inputs and compl

Features

  • Y Y Y Y Y Y Complementary outputs Direct overriding (data) inputs Gated clock inputs Parallel-to-serial data conversion Typical frequency 35 MHz Typical power dissipation 105 mW Connection Diagram Dual-In-Line Package TL F 6399.
  • 1 Order Number DM54LS165J DM54LS165W DM74LS165WM or DM74LS165N See NS Package Number J16A M16B N16E or W16A Function Table Inputs Shift Load L H H H H Clock Inhibit X L L L H Clock X L Serial X X H L X Parallel A H a h X X X X QA a QA0 H L QA0 Internal Out.

📥 Download Datasheet

Datasheet preview – DM54LS165

Datasheet Details

Part number DM54LS165
Manufacturer National Semiconductor
File Size 140.50 KB
Description 8-Bit Parallel In/Serial Output Shift Registers
Datasheet download datasheet DM54LS165 Datasheet
Additional preview pages of the DM54LS165 datasheet.

📁 Similar Datasheet

  • DM54LS47 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS48 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54LS49 - BCD/7-Segment Decoder/Driver (MSI)
  • DM54L89A - 64-BIT READ/WRITE MEMORIES (ETC)
  • DM54141 - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM54155 - Dual 2-Line to 4-Line Decoders/Demultiplexers (ETC)
  • DM5441A - BCD / DECIMAL DECODERS / DRIVERS (MSI)
  • DM5446A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5447A - BCD/7-Segment Decoder/Driver (MSI)
  • DM5448 - BCD/7-Segment Decoder/Driver (MSI)
Other Datasheets by National Semiconductor
  • DM54LS161A - Synchronous 4-Bit Binary Counters
  • DM54LS163A - Synchronous 4-Bit Binary Counters
  • DM54LS164 - 8-Bit Serial In/Parallel Out Shift Registers
  • DM54LS169A - Synchronous 4-Bit Up/Down Binary Counter
  • DM54LS10 - Triple 3-Input NAND Gates
  • DM54LS109A - Dual Positive-Edge-Triggered J-K Flip-Flops with Preset/ Clear/ and Complementary Outputs
  • DM54LS11 - Triple 3-Input AND Gates
  • DM54LS112A - NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS

Full PDF Text Transcription

Click to expand full text
DM54LS165 DM74LS165 8-Bit Parallel In Serial Output Shift Registers May 1992 DM54LS165 DM74LS165 8-Bit Parallel In Serial Output Shift Registers General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked Parallel-in access is made available by eight individual direct data inputs which are enabled by a low level at the shift load input These registers also feature gated clock inputs and complementary outputs from the eighth bit Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock-inhibit function Holding either of the clock inputs high inhibits clocking and holding either clock input low with the load input high enables the other clock input The clock-inhibit input should be ch
Published: |