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DM54S195 - 4-Bit Parallel Access Shift Registers

Datasheet Summary

Description

These 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear All inputs are buffered to lower the input drive requirements The registers have two modes of operation Parallel (broadside) load Shift (in the direction QA toward

Features

  • Y Synchronous parallel load Y Positive-edge-triggered clocking Y Parallel inputs and outputs from each flip-flop Y Direct overriding clear Y J and K inputs to first stage Y Complementary outputs from last stage Y For use in high-performance accumulators processors serial-to-parallel parallel-to-serial converters Y Typical clock frequency 105 MHz Y Typical power dissipation 350 mW Connection Diagram Dual-In-Line Package Order Number DM54S195J or DM74S195N See NS Package Number J16A or N16E TL.

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Datasheet Details

Part number DM54S195
Manufacturer National Semiconductor
File Size 117.59 KB
Description 4-Bit Parallel Access Shift Registers
Datasheet download datasheet DM54S195 Datasheet
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DM54S195 DM74S195 4-Bit Parallel Access Shift Registers June 1989 DM54S195 DM74S195 4-Bit Parallel Access Shift Registers General Description These 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear All inputs are buffered to lower the input drive requirements The registers have two modes of operation Parallel (broadside) load Shift (in the direction QA toward QD) Parallel loading is accomplished by applying the four bits of data and taking the shift load control input low The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input During loading serial data flow is inhibited Shifting is accomplished synchronously when the shift load control inp
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