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DM74LS155 - Dual 2-Line to 4-Line Decoders/Demultiplexers

General Description

These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package When both sections are enabled by the strobes the common address inputs sequentially select and route associated input data to the appropriate output of

Key Features

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📁 Similar Datasheet

Part Number Description Manufacturer
DM74LS155 Dual 2-Line to 4-Line Decoders/Demultiplexers Fairchild Semiconductor
DM74LS151 1-of-8 Line Data Selector/Multiplexer Fairchild Semiconductor
DM74LS153 Dual 1-of-4 Line Data Selectors/Multiplexers Fairchild Semiconductor
DM74LS154 4-Line to 16-Line Decoder/Demultiplexer Fairchild Semiconductor
DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers Fairchild Semiconductor

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DM74LS151 Data Selector/Multiplexer
DM74LS153 Dual 4-Line to 1-Line Data Selectors/Multiplexers
DM74LS154 4-Line to 16-Line Decoders/Demultiplexers
DM74LS156 Dual 2-Line to 4-Line Decoders/Demultiplexers
DM74LS157 Quad 2-Line to 1-Line Data Selectors/Multiplexers

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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54LS155 DM54LS155 DM74LS155 54LS156 DM54LS156 DM74LS156 Dual 2-Line to 4-Line Decoders Demultiplexers June 1989 54LS155 DM54LS155 DM74LS155 54LS156 DM54LS156 DM74LS156 Dual 2-Line to 4-Line Decoders Demultiplexers General Description These TTL circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package When both sections are enabled by the strobes the common address inputs sequentially select and route associated input data to the appropriate output of each section The individual strobes permit activating or inhibiting each of the 4-bit sections as desired Data applied to input C1 is inverted at its outputs and data applied at C2 is true through its outputs The inverter following the C1 data input permits use a