Datasheet4U Logo Datasheet4U.com

DM74LS174 - Hex/Quad D Flip-Flops

Description

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary outputs from each flip-flop Information at the D inputs meeting the setup time requirements is transferred to the Q outpu

Features

  • Y Y Y Y Y Y Y Y LS174 contains six flip-flops with single-rail outputs LS175 contains four flip-flops with double-rail outputs Buffered clock and direct clear inputs Individual data input to each flip-flop.

📥 Download Datasheet

Datasheet preview – DM74LS174

📁 Similar Datasheet

  • DM74LS174 - Hex/Quad D-Type Flip-Flops (Fairchild Semiconductor)
  • DM74LS175 - Hex/Quad D-Type Flip-Flops (Fairchild Semiconductor)
  • DM74LS10 - Triple 3-Input NAND Gate (Fairchild Semiconductor)
  • DM74LS109A - Dual Positive-Edge-Triggered J-K Flip-Flop (Fairchild Semiconductor)
  • DM74LS11 - Triple 3-Input AND Gate (Fairchild Semiconductor)
  • DM74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop (Fairchild Semiconductor)
  • DM74LS123 - Dual Retriggerable One-Shot (Fairchild Semiconductor)
  • DM74LS125A - Quad 3-STATE Buffer (Fairchild Semiconductor)
  • DM74LS126A - Quad 3-STATE Buffer (Fairchild Semiconductor)
  • DM74LS132 - Quad 2-Input NAND Gate (Fairchild Semiconductor)
Other Datasheets by National Semiconductor

Full PDF Text Transcription

Click to expand full text
54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear June 1989 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad (175) versions feature complementary outputs from each flip-flop Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse When the clock input is at either the high or low level the D input signal has no effect at the output Feat
Published: |