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DM74LS379 - Quad Parallel Register

General Description

The LS379 is a 4-bit register with buffered common Enable This device is similar to the LS175 but

Key Features

  • the common Enable rather than common Master Reset Features Y Y Y Y Edge-triggered D-type inputs Buffered positive edge-triggered clock Buffered common enable input True and complement outputs Connection Diagram Dual-In-Line Package Logic Symbol TL F 10186.
  • 2 TL F 10186.
  • 1 VCC e Pin 16 GND e Pin 8 Order Number 54LS379DMQB 54LS379FMQB 54LS379LMQB DM74LS379M or DM74LS379N See NS Package Number E20A J16A M16A N16E or W16A Pin Names E D0.
  • D3 CP Q0.
  • Q3 Q0.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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54LS379 DM74LS379 Quad Parallel Register with Enable June 1989 54LS379 DM74LS379 Quad Parallel Register with Enable General Description The LS379 is a 4-bit register with buffered common Enable This device is similar to the LS175 but features the common Enable rather than common Master Reset Features Y Y Y Y Edge-triggered D-type inputs Buffered positive edge-triggered clock Buffered common enable input True and complement outputs Connection Diagram Dual-In-Line Package Logic Symbol TL F 10186 – 2 TL F 10186 – 1 VCC e Pin 16 GND e Pin 8 Order Number 54LS379DMQB 54LS379FMQB 54LS379LMQB DM74LS379M or DM74LS379N See NS Package Number E20A J16A M16A N16E or W16A Pin Names E D0–D3 CP Q0–Q3 Q0 – Q3 Description Enable Input (Active LOW) Data Inputs Clock Pulse Input (Active Rising Edg