Description
These 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear All inputs are buffered to lower the input drive requirements The registers have two modes of operation
Parallel (broadside) load
Shift (in the direction QA toward
Features
- Y Synchronous parallel load Y Positive-edge-triggered clocking Y Parallel inputs and outputs from each flip-flop Y Direct overriding clear Y J and K inputs to first stage Y Complementary outputs from last stage Y For use in high-performance
accumulators processors serial-to-parallel parallel-to-serial converters Y Typical clock frequency 105 MHz Y Typical power dissipation 350 mW
Connection Diagram
Dual-In-Line Package
Order Number DM54S195J or DM74S195N See NS Package Number J16A or N16E
TL.
DM74S195 Datasheet
