DM8556 Datasheet | National Semiconductor

Description These circuits are synchronous edge-sensitive fully-programmable 4-bit counters The counters feature both conventional totem-pole and TRI-STATE outputs such that when the outputs are in the high impedance mode they can be used to enter data from the bus lines In addition the clear input operates pletely independent of all other inputs During the programming operation data is loaded into the flip-flops on the positive-going edge of the clock pulse To facilitate cascading of these counters the MAX COUNT output can be tied directly into the count enable input of the next counter Features Y Y Y Y Y Typical clock frequency 35 MHz TRI-STATE outputs Fully independent clear Synchronous loading Cascading circuitry provided internally Connection Diagram Dual-In-Line Package TL F 6588 - 1 Order Number DM7556J or DM8556N See NS Package Number J16A or N16A Function Table Control Inputs LOAD H H H H L H H CE X X X X H L L CLK X X L L OD L H L H L L H Reset H H L L L L L I OA L Z QA0 Z a Z I O Ports I OB I OC I OD L Z QD0 Z d Z QA L L QA0 QA0 A Active Outputs QB QC QD L L QD0 QD0 D u u u L L Z Z QB0 QC0 Z Z b c COUNT Z Z L L L L QB0 QC0 QB0 QC0 B C COUNT COUNT The I O pins are used as inputs when they are TRI-STATED and the LOAD input is Low They are outputs and active when LOAD input is High and OD is Low H e High Level (Steady State) L e Low Level (Steady State) X e Don’t Care including transitions a b c d e The level of the steady state input at inputs A B C D respectively QA0 QB0 QC0 QD0 e The level of QA QB QC QD respectively before the indicated steady state input conditions were established TRI-STATE is a registered trademark of the National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 6588 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V...