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DM8806 - high speed MOS to TTL level converters

Download the DM8806 datasheet PDF. This datasheet also covers the DM8802 variant, as both devices belong to the same high speed mos to ttl level converters family and are provided as variant models within a single manufacturer datasheet.

General Description

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The DM7802/DM8802, DM7806/DM8806 are high speed MOS to TTL level converters.

These circuits act as an interface level converter between MOS -and TTL logic devices.

It consists of two 1-input converters with common strobe input to inhibit "0" entry when strobe is high.

Key Features

  • Very low output impedance - high drive ability.
  • High impedance output state which allows many outputs to be connected to a common bus line.
  • Average power dissipation 110' mW per converter logic and connection diagrams c :s:: aoI . N C :s:: 00 o00 N C :s:: . aoec. . n. I. . :s:: 00 oe0n0 IN. (.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DM8802-NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DM8800 Dual Voltage Translator
DM8802 high speed MOS to TTL level converters
DM8810 quad 2-input TTL-MOS interface gate
DM8811 quad 2-input TTL-MOS interface gate
DM8812 TTL-MOS hex inverter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
S~nse Amplifiers OM7802/0M8802. OM7806/0M,8806 high speed MOS to TTL level converters general description* The DM7802/DM8802, DM7806/DM8806 are high speed MOS to TTL level converters. These circuits act as an interface level converter between MOS -and TTL logic devices. It consists of two 1-input converters with common strobe input to inhibit "0" entry when strobe is high. It allows parallel entry when strobe is low and the internal latch is preset by the common preset input. TR 1STATE@ output logic is implemented in this circuit to facilitate high speed time sharing of decoder-drivers, fast random-access (or sequential) memory arrays, etc. • Also see LM3625.