DP83846A Datasheet | National Semiconductor

Description The DP83846A is a full feature single Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols over Category 3 (10 Mb/s) or Category 5 Unsheilded twisted pair cables. The DP83846A is designed for easy implementation of 10/100 Mb/s Ethernet home or office solutions. It interfaces to Twisted Pair media via an external transformer. This device interfaces directly to MAC devices through the IEEE 802.3u standard Media Independent Interface (MII) ensuring interoperability between products from different vendors. Features - - - - IEEE 802.3 ENDEC, 10BASE-T transceivers and filters IEEE 802.3u PCS, 100BASE-TX transceivers and filters IEEE 802.3 pliant Auto-Negotiation Output edge rate control eliminates external filtering for Transmit outputs Base Line Wander pensation 5V/3.3V MAC interface IEEE 802.3u MII (16 pins/port) LED support (Link, Rx, Tx, Duplex, Speed, Collision) Single register access for plete PHY status 10/100 Mb/s packet loopback BIST (Built in Self Test) Low-power 3.3V, 0.35um CMOS technology Power consumption < 495m W (typical) 5V tolerant I/Os 80-pin LQFP package (12w) x (12l) x (1.4h) mm - - - - - The DP83846A utilizes on chip Digital Signal Processing - (DSP) technology and digital Phase Lock Loops (PLLs) for - robust performance under all operating conditions, - enhanced noise immunity, and lower external ponent - count when pared to analog solutions. - Applications - Network Interface Cards - PCMCIA Cards System Diagram Magnetics Ethernet MAC MII 10/100 Mb/s Ds PHYTER RJ-45 10BASE-T or 100BASE-TX 25 MHz Clock Status LEDs Typical Ds PHYTER application ©2002 National Semiconductor Corporation .national. HARDWARE CONFIGURATION PINS (AN_EN, AN0, AN1) (PAUSE_EN) (LED_CFG, PHYAD) RXD[3:0] TXD[3:0] MDIO MII INTERFACE/CONTROL RX_ER RX_CLK TX_CLK SERIAL MANAGEMENT RX_DV TX_ER TX_EN COL CRS RX_CLK TX_DATA TX_DATA TX_CLK REGISTERS MII PHY ADDRESS NRZ...