DS26C32AM Datasheet | National Semiconductor

DS26C32AT/DS26C32AM Quad Differential Line Receiver June 1998 DS26C32AT/DS26C32AM Quad Differential Line Receiver General Description The DS26C32A is a quad differential line receiver designed to meet the RS-422, RS-423, and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission, while retaining the low power characteristics of CMOS. The DS26C32A has an input sensitivity of 200 m V over the mon mode input voltage range of ±7V. The DS26C32A Features internal pull-up and pull-down resistors which prevent output oscillation on unused channels. The DS26C32A provides an enable and disable function mon to all four receivers, and Features TRI-STATE ® outputs with 6 m A source and sink capability. This product is pin patible with the DS26LS32A and the AM26LS32. Features n CMOS design for low power n ±0.2V sensitivity over input mon mode voltage range n Typical propagation delays: 19 ns n Typical input hysteresis: 60 m V n Inputs won’t load...