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DS26LS33C - Quad Differential Line Receivers

This page provides the datasheet information for the DS26LS33C, a member of the DS26LS33AC Quad Differential Line Receivers family.

Description

The DS26LS32 and DS26LS32A are quad differential line receivers designed to meet the RS-422 RS-423 and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission The DS26LS32 and DS26LS32A have an input sensitivity of 200 mV over the input voltage range of g 7V and the DS2

Features

  • TRI-STATE outputs with 8 mA sink capability Constructed using low power Schottky processing these devices are available over the full military and commerical operating temperature ranges Features Y Y Y Y Y Y Logic Diagram r e . n a ww 0 TL F 5255.
  • 2 TL F 5255 ua ENABLE HI-Z e TRI-STATE t e n Truth Table 1 See Note Below Connection Diagram F w C Dual-In-Line Package Top View ce. TL F 5255.
  • 1 8 c T ENABLE Input X RRD-B30M36 Printed in U S A Y om VID t VTH (Max) VID s V.

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Datasheet preview – DS26LS33C

Datasheet Details

Part number DS26LS33C
Manufacturer National Semiconductor
File Size 200.54 KB
Description Quad Differential Line Receivers
Datasheet download datasheet DS26LS33C Datasheet
Additional preview pages of the DS26LS33C datasheet.
Other Datasheets by National Semiconductor

Full PDF Text Transcription

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DS26LS32C DS26LS32M DS26LS32AC DS26LS33C DS26LS33M DS26LS33AC Quad Differential Line Receivers January 1996 DS26LS32C DS26LS32M DS26LS32AC DS26LS33C DS26LS33M DS26LS33AC Quad Differential Line Receivers General Description The DS26LS32 and DS26LS32A are quad differential line receivers designed to meet the RS-422 RS-423 and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission The DS26LS32 and DS26LS32A have an input sensitivity of 200 mV over the input voltage range of g 7V and the DS26LS33 and DS26LS33A have an input sensitivity of 500 mV over the input voltage range of g 15V Both the DS26LS32A and DS26LS33A differ in function from the popular DS26LS32 and DS26LS33 in that input pull-up and pull-down resistors are included which prevent output oscillatio
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