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DS3486 - Quad RS-422/ RS-423 Line Receiver

Download the DS3486 datasheet PDF. This datasheet also covers the DS3 variant, as both devices belong to the same quad rs-422/ rs-423 line receiver family and are provided as variant models within a single manufacturer datasheet.

General Description

National’s quad RS-422, RS-423 receiver

Key Features

  • four independent receivers which comply with EIA Standards for the electrical characteristics of balanced/unbalanced voltage digital interface circuits. Receiver outputs are 74LS compatible, TRI-STATE ® structures which are forced to a high impedance state when the appropriate output control pin reaches a logic zero condition. A PNP device buffers each output control pin to assure minimum loading for either logic one or logic zero inputs. In addition, each receiver has internal hysteresis circui.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS3-486.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DS3486 Line Receiver Texas Instruments
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DS3430 5-Port Pilot Solenoid Valve Body Ported Type / Base Ported Type TPC

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DS3487 Quad TRI-STATE Line Driver
DS34C86T Quad CMOS Differential Line Receiver
DS34C87T CMOS Quad TRISTATE Differential Line Driver
DS34F86 (DS34F86 / DS35F86) RS-422/RS-423 Quad Line Receiver
DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS3486 Quad RS-422, RS-423 Line Receiver May 1998 DS3486 Quad RS-422, RS-423 Line Receiver General Description National’s quad RS-422, RS-423 receiver features four independent receivers which comply with EIA Standards for the electrical characteristics of balanced/unbalanced voltage digital interface circuits. Receiver outputs are 74LS compatible, TRI-STATE ® structures which are forced to a high impedance state when the appropriate output control pin reaches a logic zero condition. A PNP device buffers each output control pin to assure minimum loading for either logic one or logic zero inputs. In addition, each receiver has internal hysteresis circuitry to improve noise margin and discourage output instability for slowly changing input waveforms.