DS50EV401 Datasheet | National Semiconductor

DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer June 8, 2010 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer General Description The DS50EV401 is a low power, programmable equalizer specifically designed to reduce inter-symbol interference (ISI) induced by a variety of interconnect media. In all modes, the equalizer can operate, error free, with an input eye that is pletely closed by interconnect ISI. The MODE control, allows the user to select between equalization settings for 8.0 Gbps operation or 2.5 Gbps / 5.0 Gbps operation. The DS50EV401 uses Current-mode logic (CML) on both input and output ports, which provide constant 50 ohm singleended impedance to AC ground. Differential signaling is implemented through out the entire signal path to minimize supply induced jitter. The DS50EV401 is available in a 7mm x 7mm 48-pin leadless LLP package, and is powered from a single power supply of either 3.3 or 2.5V. Features - Automatic power management on an individual lane basis - Data rate optimized equalization - Operates over 7 meter of 24 AWG Twin-ax Cables up to 8 Gbps - Typical residual deterministic jitter: - 0.18 UI @ 8 Gbps w/ 30” of FR4 - 0.18 UI @ 5 Gbps w/ 40” of FR4 - 0.16 UI @ 2.5 Gbps w/ 40” of FR4 - 8 k V HBM ESD protection - -40 to 85°C operating temperature range - 7 mm x 7 mm 48-pin leadless LLP package - Single power supply of either 3.3V or 2.5V - Low power (typically 95 m W per channel at 2.5V VDD) Application Diagram © 2010 National Semiconductor Corporation 300505 .national. Pin Descriptions Pin Name Pin Number I/O, Type Description HIGH SPEED DIFFERENTIAL I/O IN_0+ IN_0- 1 I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω 2 terminating resistor connects IN_0+ to VDD and IN_0- to VDD. IN_1+...