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DS8907 Datasheet Phase-locked Loop Frequency Synthesizer

Manufacturer: National Semiconductor (now Texas Instruments)

Overview: DS8907 AM FM Digital Phase-Locked Loop Frequency Synthesizer July 1986 DS8907 AM FM Digital Phase-Locked Loop Frequency.

General Description

The DS8907 is a PLL synthesizer designed specifically for use in AM FM radios It contains the reference oscillator a phase parator a charge pump a 120 MHz ECL I2L dual modulus programmable divider and an 18-bit shift register latch for serial data entry The device is designed to operate with a serial data controller generating the necessary division codes for each frequency and logic state information for radio function inputs outputs The Colpitts reference oscillator for the PLL operates at 4 MHz A chain of dividers is used to generate a 500 kHz clock signal for the external controller Additional dividers generate a 25 kHz reference signal for FM and a 10 kHz reference signal for AM One of these reference signals is selected by the data from the controller for use by the phase parator Data is transferred between the frequency synthesizer and the controller via a 3 wire bus system This consists of a data input line an enable line and a clock line When the enable line is low data can be shifted from the controller into the frequency synthesizer When the enable line is transitioned from low to high data entry is disabled and data present in the shift register is latched From the controller 20-bit data stream the first 2 bits address the device permitting other devices to share the same bus Of the remaining 18-bit data word the next 13 bits are used for the PLL divide code The remaining 5 bits are connected via latches to output pins These 5 bits can be used to drive radio functions such as gain mute FM AM and stereo only These outputs are open collector Bit 16 is used internally to select the AM or FM local oscillator input and to select between the 10 kHz and 25 kHz reference A high level at bit 16 indicates FM and a low level indicates AM The PLL consists of a 13-bit programmable I2L divider an ECL phase p

Key Features

  • Y Y Y Y Y Y Y Uses inexpensive 4 MHz reference crystal FIN capability greater than 120 MHz allows direct synthesis at FM frequencies FM resolution of 25 kHz allows usage of 10 7 MHz ceramic filter distribution Serial data entry for simplified control 50 Hz output for ‘‘time-of-day’’ reference driven from separate low power VCCM 5-open collector buffered outputs for controlling various radio functions Separate AM and FM inputs AM input has 15 mV (typical) hysteresis Connection Diagram Dual.

More Datasheets from National Semiconductor (now Texas Instruments)

Part Number Description
DS8911 Sound Up-Conversion Frequency Synthesizer
DS8913 Sound Up-Conversion Frequency Synthesizer
DS8921 Differential Line Driver and Receiver Pair
DS8921A Differential Line Driver and Receiver Pair
DS8921AT Differential Line Driver and Receiver Pair
DS8922 TRI-STATE RS-422 Dual Differential Line Driver and Receiver Pairs
DS8922A RS-422 Dual Differential Line Driver and Receiver Pairs
DS8923A RS-422 Dual Differential Line Driver and Receiver Pairs
DS8925 LocalTalk Dual Driver/Triple Receiver
DS8935 LocalTalk Dual Driver/Triple Receiver

DS8907 Distributor