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DS90C124 - 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

General Description

The DS90C241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

Key Features

  • pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. n User selectable clock edge for parallel data on both Transmitter and Receiver n Internal DC Balancing encode/decode.
  • Supports AC-coupling interface with no external coding required n Individual power-down controls for both Transmitter and Receiver n Embedded clock CDR (clock and data recovery) on Receiver and no external source of.

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DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2006 DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS90C241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS90C241/124 incorporates LVDS signaling on the high-speed I/O.