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DS90C241 - 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Download the DS90C241 datasheet PDF. This datasheet also covers the DS90C124 variant, as both devices belong to the same 5-35mhz dc-balanced 24-bit lvds serializer and deserializer family and are provided as variant models within a single manufacturer datasheet.

General Description

The DS90C241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

Key Features

  • pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. n User selectable clock edge for parallel data on both Transmitter and Receiver n Internal DC Balancing encode/decode.
  • Supports AC-coupling interface with no external coding required n Individual power-down controls for both Transmitter and Receiver n Embedded clock CDR (clock and data recovery) on Receiver and no external source of.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS90C124_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DS90C241 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer/Deserializer Texas Instruments
DS90C031B LVDS Quad CMOS Differential Line Driver Texas Instruments
DS90C031QML LVDS Quad CMOS Differential Line Driver Texas Instruments
DS90C032 LVDS Quad CMOS Differential Line Receiver Texas Instruments
DS90C032B LVDS Quad CMOS Differential Line Receiver Texas Instruments

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DS90C2501 Transmitter
DS90C031 LVDS Quad CMOS Differential Line Driver
DS90C031B LVDS Quad CMOS Differential Line Driver
DS90C032 LVDS Quad CMOS Differential Line Receiver
DS90C032B LVDS Quad CMOS Differential Line Receiver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2006 DS90C241/DS90C124 5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS90C241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS90C241/124 incorporates LVDS signaling on the high-speed I/O.