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DS90CR287 - 28-Bit Channel Link

General Description

The DS90CR287 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Key Features

  • n n n n n n n n n n n n n 20 to 85 MHZ shift clock support 50% duty cycle on receiver output clock Best.
  • in.
  • Class Set & Hold Times on TxINPUTs Low power consumption ± 1V common mode range (around +1.2V) Narrow bus reduces cable size and cost Up to 2.38 Gbps throughput Up to 297.5 Megabytes/sec bandwidth 345 mV (typ) swing LVDS devices for low EMI PLL requires no external components Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead TSSOP package.

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📁 Similar Datasheet

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DS90CR287 +3.3V Rising Edge Data Strobe LVDS Texas Instruments
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DS90CR286A 3.3-V Rising Edge Data Strobe LVDS Receiver Texas Instruments
DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver Texas Instruments

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
DS90CR281 28-Bit Channel Link
DS90CR282 28-Bit Channel Link
DS90CR283 28-Bit Channel Link
DS90CR284 28-Bit Channel Link
DS90CR285 +3.3V Rising Edge Data Strobe LVDS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ October 1999 DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ General Description The DS90CR287 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 85 MHZ, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHZ clock, the data throughput is 2.38 Gbit/s (297.