DS90CR583 Datasheet PDF (LVDS 24-Bit Color Flat Panel Display Link) | Download National Semiconductor DS90CR583

DS90CR583 - LVDS 24-Bit Color Flat Panel Display Link

Description

The DS90CR583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Features

n n n n n n n n n n n n n 20 to 65 MHz shift clk support Up to 227 Mbytes/s bandwidth Cable size is reduced to save cost 290 mV swing LVDS devices for low EMI Low power CMOS design ( < 550 mW typ) Power-down mode saves power ( < 0.25 mW) PLL requires no external components Low profile 56-lead TSSOP package Rising edge data strobe Compatible with TIA/EIA-644 LVDS standard Single pixel per clock XGA (1024 x 768) Supports VGA, SVGA, XGA and higher 1.8 Gbps throughput Block Diagrams DS90CR583 DS90C.

Datasheet Details

Part number	DS90CR583
Manufacturer	National Semiconductor
File Size	318.09 KB
Description	LVDS 24-Bit Color Flat Panel Display Link
Datasheet	DS90CR583 Datasheet
Additional preview pages of the DS90CR583 datasheet.

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Full PDF Text Transcription

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DS90CR583/DS90CR584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz July 1997 DS90CR583/DS90CR584 LVDS 24-Bit Color Flat Panel Display (FPD) Link— 65 MHz General Description The DS90CR583 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR584 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CONTROL) are transmitted at a rate of 455 Mbps per LVDS data channel.

Published: Mar 30, 2005 |