Datasheet4U Logo Datasheet4U.com

DS90LV048A - 3V LVDS Quad CMOS Differential Line Receiver

Datasheet Summary

Description

The DS90LV048A is a quad CMOS flow-through differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

Features

  • n n n n n n n n n n n n n n > 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 2.7 ns maximum propagation delay 3.3V power supply design High impedance LVDS inputs on power down Low Power design (40mW 3.3V static) Interoperable with existing 5V LVDS drivers Accepts small swing (350 mV typical) differential signal levels Supports open, short and terminated input fail-safe Conforms to ANSI/TIA/.

📥 Download Datasheet

Datasheet preview – DS90LV048A

Datasheet Details

Part number DS90LV048A
Manufacturer National Semiconductor
File Size 245.58 KB
Description 3V LVDS Quad CMOS Differential Line Receiver
Datasheet download datasheet DS90LV048A Datasheet
Additional preview pages of the DS90LV048A datasheet.
Other Datasheets by National Semiconductor

Full PDF Text Transcription

Click to expand full text
DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver July 1999 DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver General Description The DS90LV048A is a quad CMOS flow-through differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV048A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE ® function that may be used to multiplex outputs. The receiver also supports open, shorted and terminated (100Ω) input fail-safe. The receiver output will be HIGH for all fail-safe conditions.
Published: |