LM4310
Key Features
- 24-bit or 18-bit RGB Display Interface
- Supports QVGA to > 640 x 480 VGA Resolutions
- MPL-2 Differential Physical Layer
- Internal 100 Ω Termination and CM Filter
- Glitch filter on control signals (DE, VS & HS)
- Parity / Payload error reporting pin and data re-circulator Bufferless displays from QVGA (320 x 240) up to >VGA (640 x 480) pixels are supported. The Deserializer also provides a glitch filter on the three control signals (DE, VS and HS). Glitches of 1 or 2 PCLKs wide are filtered out by the Deserializer to prevent flicker on the display.
- Low Power Consumption
- Receiver output drive strength control (RDS)
- Frame Sequence bits automatically resync upon data or clock error
- Power down mode reduces power to < 10 µA Performance of the serial link can be checked by use of the System Benefits parity/packet error reporting pin that monitors the serial pay- load odd parity bit and reports errors. The LM4310 DES and LM4312 SER implements the physical layer of the MPL-2 Interface and features robust common- .
