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LMH0051 - DVB-ASI SDI Deserializer

This page provides the datasheet information for the LMH0051, a member of the LMH0041 DVB-ASI SDI Deserializer family.

Description

The LMH0041 family of products provide a very simple 1:5 deserializer and receiver function.

The device is intended to be paired with an FPGA host which will receive the raw 5 bit data words and will decode the data appropriately such that a SMPTE standard signal may be recovered.

Features

  • LVDS Interface Dual multiplexed inputs No external VCO or clock required Loopthrough with Cable Driver SMBus configuration interface 48 pin LLP package.

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Datasheet preview – LMH0051

Datasheet Details

Part number LMH0051
Manufacturer National Semiconductor
File Size 140.44 KB
Description DVB-ASI SDI Deserializer
Datasheet download datasheet LMH0051 Datasheet
Additional preview pages of the LMH0051 datasheet.

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Full PDF Text Transcription

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LMH0341, LMH0041, LMH0071, LMH0051 3G, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface ADVANCE INFORMATION April 2007 LMH0341, LMH0041, LMH0071, LMH0051 3G, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface General Description The LMH0041 family of products provide a very simple 1:5 deserializer and receiver function. The device is intended to be paired with an FPGA host which will receive the raw 5 bit data words and will decode the data appropriately such that a SMPTE standard signal may be recovered. The devices are designed to receive data compliant with DVB-ASI, SMPTE 259M, SMPTE 292M and/or SMPTE 424M. The interface between the LMH0041 and the FPGA consists of a 5 bit wide LVDS bus, an LVDS clock and an SMBus interface.
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