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LMK01020 - (LMK01000 - LMK01020) 1.6 GHz High Performance Clock Buffer

Download the LMK01020 datasheet PDF. This datasheet also covers the LMK01000 variant, as both devices belong to the same (lmk01000 - lmk01020) 1.6 ghz high performance clock buffer family and are provided as variant models within a single manufacturer datasheet.

General Description

The LMK01000/LMK01010/LMK01020 family provides an easy way to divide and distribute high performance clock signals throughout the system.

Key Features

  • two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains. Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC.
  • ). Features.
  • 30 fs additive jitter (100 Hz to 20 MHz).
  • Dual clock inputs.
  • Programmable output channels (0 to 1600 MHz).
  • LMK01000: 3 LVDS outp.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LMK01000_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
LMK01000/LMK01010/LMK01020 1.6 GHz High Performance Clock Buffer, Divider, and Distributor www.DataSheet4U.com March 6, 2008 LMK01000/LMK01010/LMK01020 1.6 GHz High Performance Clock Buffer, Divider, and Distributor General Description The LMK01000/LMK01010/LMK01020 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-inclass noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners. The LMK01000/LMK01010/LMK01020 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.