MM54C200 Datasheet PDF - National Semiconductor Random Access Read/Write Memory Specs

MM54C200 - Random Access Read/Write Memory

Datasheet Summary

Description

The MM54C200 MM74C200 is a 256-bit random access read write memory Inputs consist of eight address lines and three chip enables The eight binary address inputs are decoded internally to select each of the 256 locations The internal address register latches and address information are on the positive

Datasheet Details

Part number	MM54C200
Manufacturer	National Semiconductor
File Size	332.72 KB
Description	Random Access Read/Write Memory
Datasheet	MM54C200 Datasheet
Additional preview pages of the MM54C200 datasheet.

📁 Similar Datasheet

MM54C20 - Quad 2-Input NAND Gate / Quad 2-Input NOR Gate / Hex Inverter / Triple 3-Input NAND Gate / Dual 4-Input NAND Gate (National)

MM54C221 - Dual Monostable Multivibrator (National)

MM54C240 - Octal Buffers and Line Drivers with TRI-STATE Outputs (National)

MM54C244 - Octal Buffers and Line Drivers with TRI-STATE Outputs (National)

MM54C00 - Quad 2-Input NAND Gate / Quad 2-Input NOR Gate / Hex Inverter / Triple 3-Input NAND Gate / Dual 4-Input NAND Gate (National)

MM54C02 - Quad 2-Input NAND Gate / Quad 2-Input NOR Gate / Hex Inverter / Triple 3-Input NAND Gate / Dual 4-Input NAND Gate (National)

MM54C04 - Quad 2-Input NAND Gate / Quad 2-Input NOR Gate / Hex Inverter / Triple 3-Input NAND Gate / Dual 4-Input NAND Gate (National)

MM54C08 - Quad 2-Input AND Gate (National)

MM54C10 - Quad 2-Input NAND Gate / Quad 2-Input NOR Gate / Hex Inverter / Triple 3-Input NAND Gate / Dual 4-Input NAND Gate (National)

MM54C14 - Hex Schmitt Trigger (National)

Full PDF Text Transcription

Click to expand full text

Obsolete MM54C200 MM74C200 256-Bit TRI-STATE Random Access Read Write Memory February 1988 MM54C200 MM74C200 256-Bit TRI-STATE Random Access Read Write Memory General Description The MM54C200 MM74C200 is a 256-bit random access read write memory Inputs consist of eight address lines and three chip enables The eight binary address inputs are decoded internally to select each of the 256 locations The internal address register latches and address information are on the positive to negative edge of CE3 The TRISTATE data output line working in conjunction with CE1 or CE2 inputs provides for easy memory expansion Address Operation Address inputs must be stable tSA prior to the positive to negative transition of CE3 It is therefore unnecessary to hold address information stable for more than

Published: Aug 6, 2018 |