Datasheet4U Logo Datasheet4U.com

MM54C200 - Random Access Read/Write Memory

General Description

The MM54C200 MM74C200 is a 256-bit random access read write memory Inputs consist of eight address lines and three chip enables The eight binary address inputs are decoded internally to select each of the 256 locations The internal address register latches and address information are on the positive

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MM54C20 Quad 2-Input NAND Gate / Quad 2-Input NOR Gate / Hex Inverter / Triple 3-Input NAND Gate / Dual 4-Input NAND Gate National
MM54C221 Dual Monostable Multivibrator National
MM54C240 Octal Buffers and Line Drivers with TRI-STATE Outputs National
MM54C244 Octal Buffers and Line Drivers with TRI-STATE Outputs National
MM54C00 Quad 2-Input NAND Gate / Quad 2-Input NOR Gate / Hex Inverter / Triple 3-Input NAND Gate / Dual 4-Input NAND Gate National

Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
MM54C150 16-Line to 1-Line Multiplexer
MM54C173 TRI-STATE Quad D Flip-Flop
MM54C30 8-Input NAND Gate
MM54C32 Quad 2-Input OR Gate
MM54C373 Octal D-Type Latch

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Obsolete MM54C200 MM74C200 256-Bit TRI-STATE Random Access Read Write Memory February 1988 MM54C200 MM74C200 256-Bit TRI-STATE Random Access Read Write Memory General Description The MM54C200 MM74C200 is a 256-bit random access read write memory Inputs consist of eight address lines and three chip enables The eight binary address inputs are decoded internally to select each of the 256 locations The internal address register latches and address information are on the positive to negative edge of CE3 The TRISTATE data output line working in conjunction with CE1 or CE2 inputs provides for easy memory expansion Address Operation Address inputs must be stable tSA prior to the positive to negative transition of CE3 It is therefore unnecessary to hold address information stable for more than