MM74HC85 Datasheet | National Semiconductor

MM54HC85 MM74HC85 4-Bit Magnitude parator November 1995 MM54HC85 MM74HC85 4-Bit Magnitude parator General Description The MM54HC85 MM74HC85 is a 4-bit magnitude parator that utilizes advanced silicon-gate CMOS technology It is designed for high speed parison of two four bit words This circuit has eight parison inputs 4 for each word three cascade inputs (Ak B Al B A e B) and three decision outputs (Ak B Al B A e B) The result of a parison is indicated by a high level on one of the decision outputs Thus it may be determined whether one word is ‘‘greater than ’’ ‘‘less than ’’ or ‘‘equal to’’ the other word By connecting the outputs of the least significant stage to the cascade inputs of the next stage words of greater than four bits can be pared In addition the least significant stage must have a high level applied to the A e B input and a low level to the A k B and Al B inputs The parator’s outputs can drive 10 low power Schottky TTL (LS-TTL) equivalent loads and is functionally and pin equivalent to the 54LS85 74LS85 All inputs are protected from damage due to static discharge by diodes to VCC and ground Features Y Y Y Y Y Typical propagation delay 27 ns Wide operating voltage range 2 - 6V Low input current 1 m A maximum Low quiescent current 80 m A maximum (74HC Series) Output drive capability 10 LS-TTL loads Connection Diagram Dual-In-Line Package TL F 5205 - 1 Order Number MM54HC85 or MM74HC85 Truth Table paring Inputs A3 B3 A3 l B3 A3 k B3 A3 e B3 A3 e B3 A3 e B3 A3 e B3 A3 e B3 A3 e B3 A3 e B3 A3 e B3 A3 e B3 A3 e B3 A3 e B3 A2 B2 X X A2 l B2 A2 k B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A2 e B2 A1 B1 X X X X A1 l B1 A1 k B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A1 e B1 A0 B0 X X X X X X A0 l B0 A0 k B0 A0 e B0 A0 e B0 A0 e B0 A0 e B0 A0 e B0 Al B X X X X X X X X H L X H L Cascading Inputs Ak B X X X X X X X X L H X H L Ae B X X X X X X X X L L H L L Al B H L H L H L H L H L L L H Outputs Ak B L H L H...