NS16C2752 Datasheet (National Semiconductor)

Key Features

• are added to the UART device
• These features include low voltage support, 5V tolerant inputs, enhanced features, enhanced register set, and higher data rate
• The two serial channels are completely independent of each other, except for a common CPU interface and crystal input
• On power-up both channels are functionally identical to the PC16552D
• Each channel can operate with on-chip transmitter and receiver FIFO’s (in FIFO mode)
• The receiver FIFO also has additional 3 bits of error data per location
• All FIFO control logic is on-chip to minimize system software overhead and maximize system efficiency
• To improve the CPU processing bandwidth, the data transfers between the DUART and the CPU can be done using DMA controller
• Signaling for DMA transfers is done through two pins per channel (TXRDY and RXRDY)
• The RXRDY function is multiplexed on one pin with the OUT2 and BAUDOUT functions