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PC87415 - PCI-IDE DMA Master Mode Interface Controller

This page provides the datasheet information for the PC87415, a member of the PC8 PCI-IDE DMA Master Mode Interface Controller family.

Datasheet Summary

Description

The Enhanced PCI-IDE Interface is a single-chip controller packaged in a 100-pin PQFP It provides 2 IDE channels for interfacing up to 4 IDE drives or 2 IDE drives and CD-ROM directly on the PCI Local bus An enhanced DMA controller on-chip increases system performance by providing full scatter gathe

Features

  • Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y PCI bus interface for up to 4 IDE devices 33 MHz 32-bit PCI bus data path with full parity error reporting 16 7 MByte sec maximum IDE transfer rate Support for 2 IDE channels ( 2 IDE devices per channel) Primary or secondary IDE addressing (1F0x 170x) in PC compatible mode Re-mappable base registers for full PCI compliance Concurrent channel operation (PIO DMA modes) 4 Double Word write FIFO per channel 4 Double Word read prefetch FIFO per channel.

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Datasheet preview – PC87415

Datasheet Details

Part number PC87415
Manufacturer National Semiconductor
File Size 374.03 KB
Description PCI-IDE DMA Master Mode Interface Controller
Datasheet download datasheet PC87415 Datasheet
Additional preview pages of the PC87415 datasheet.

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Full PDF Text Transcription

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PC87415 PCI-IDE DMA Master Mode Interface Controller PRELIMINARY March 1996 PC87415 PCI-IDE DMA Master Mode Interface Controller 1 0 General Description The Enhanced PCI-IDE Interface is a single-chip controller packaged in a 100-pin PQFP It provides 2 IDE channels for interfacing up to 4 IDE drives or 2 IDE drives and CD-ROM directly on the PCI Local bus An enhanced DMA controller on-chip increases system performance by providing full scatter gather data transfers between IDE devices and system memory without CPU intervention Four levels of both write posting and read prefetching per channel allow the host CPU to run concurrently with IDE cycles Programmable timing functions provide maximum flexibility of timing parameters per drive for optimizing the data transfer rate per drive Both P
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