TP3057 Datasheet | National Semiconductor

TP3054 TP3057 family consists of m-law and A-law monolithic PCM CODEC filters utilizing the A D and D A conversion architecture shown in Figure 1 and a serial PCM interface The devices are fabricated using National’s advanced double-poly CMOS process (micro CMOS) The encode portion of each device consists of an input gain adjust amplifier an active RC pre-filter which eliminates very high frequency noise prior to entering a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz Also included are auto-zero circuitry and a panding coder which samples the filtered signal and encodes it in the panded m-law or A-law PCM format The decode portion of each device consists of an expanding decoder which reconstructs the analog signal from the panded m-law or A-law code a low-pass filter which corrects for the sin x x response of the decoder output and rejects signals above 3400 Hz followed by a single-ended power amplifier capable of driving low impedance loads The devices require two 1 536 MHz 1 544 MHz or 2 048 MHz transmit and receive master clocks which may be asynchronous transmit and receive bit clocks which may vary from 64 k Hz to 2 048 MHz and transmit and receive frame sync pulses The timing of the frame sync pulses and PCM data is patible with both industry standard formats Features Y plete CODEC and filtering system (BO) including Transmit high-pass and low-pass filtering Receive low-pass filter with sin x x correction Active RC noise filters m-law or A-law patible COder and DECoder Internal precision voltage reference Serial I O interface Internal auto-zero circuitry Y m-law 16-pin TP3054 Y A-law 16-pin TP3057 Y Designed for D3 D4 and CCITT applications Y g5V operation Y Low operating power typically 50 m W Y Power-down standby mode typically 3 m W Y Automatic power-down Y TTL or CMOS patible digital interfaces Y Maximizes line interface card circuit density Y Dual-In-Line or surface mount packages Y See also AN-370 ‘‘Techniques for...