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74FCT273 - Octal D Flip-Flop

General Description

The ’FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-t

Key Features

  • Y Y Y Y Y Y Y Y Y Y ICC reduced to 40 0 mA Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous master reset TTL input and output level compatible TTL levels accept CMOS levels IOL e 48 mA (Com) 32 mA (Mil) NSC 54 74FCT273 is pin and functionally equivalent to IDT 54 74FCT273 Military product compliant to MIL-STD-883 and Standard Military Drawing 5962-87656 Logic Symbols IEEE IEC Connection Diagrams Pin Assignment for DIP.

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Datasheet Details

Part number 74FCT273
Manufacturer National
File Size 168.48 KB
Description Octal D Flip-Flop
Datasheet download datasheet 74FCT273 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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54FCT 74FCT273 Octal D Flip-Flop March 1993 54FCT 74FCT273 Octal D Flip-Flop General Description The ’FCT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements Features Y Y Y Y Y Y Y Y Y Y ICC reduced to 40 0 mA Ideal buffer f