MM54C195 Datasheet | National Semiconductor

Description The MM54C195 MM74C195 CMOS 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear The following two modes of operation are possible Parallel Load Shift in direction QA towards QD Parallel loading is acplished by applying the four bits of data and taking the shift load control of input low The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input During parallel loading serial data flow is inhibited Serial shifting is acplished synchronously when the shift load control input is high Serial data for this mode is entered at the J-K inputs These inputs allow the first stage to perform as a J-K D or T-type flip flop as shown in the truth table Features Medium speed operation Y Y Y Y Y Y Y Y Y Y Y High noise immunity Low power Tenth power TTL patible Supply voltage range Synchronous parallel load Parallel inputs and outputs from each flip-flop Direct overriding clear J and K inputs to first stage plementary outputs from last stage Positive-edge triggered clocking Diode clamped inputs to protect against static charge 8 5 MHz (typ ) with 10V supply and 50 p F load 0 45 VCC (typ ) 100 n W (typ ) Drive 2 LPTTL loads 3V to 15V Applications Automotive Data terminals Instrumentation Medical electronics Alarm systems Remote metering Industrial electronics puters Schematic and Connection Diagrams Pin 8 to GND Pin 16 to VCC TL F 5902 - 1 Dual-In-Line Package TL F 5902 - 2 Top View Order Number MM54C195 or MM74C195 C1995 National Semiconductor Corporation TL F 5902 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at any Pin Operating Temperature Range MM54C195 MM74C195 b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a...