Description
These multiplexers are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement transistors They consist of four 2-input multiplexers with common select and enable inputs When the enable input is at logical ‘‘0’’ the four outputs assume the values as sele
Features
- Y Y Y Y
Supply voltage range High noise immunity Low power Tenth power TTL compatible
3V to 15V 0 45 VCC (typ ) 50 nW (typ ) Drive 2 LPTTL loads
Logic
Connection Diagrams
Dual-In-Line Package
TL F 5894.
- 2
Top View Order Number MM54C157 or MM74C157
TL F 5894.
- 1
Truth Table
Enable 1 0 0 0 0 Select X 0 0 1 1 A X 0 1 X X B X X X 0 1 Output Y 0 0 1 0 1
Guaranteed Noise Margin as a Function of VCC
74L Compatibility
TL F 5894.
- 4
TL F 5894.
- 3
C1995 Nationa.
MM74C157 Datasheet
