MM74C195 Overview
Description
The MM54C195 MM74C195 CMOS 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear The following two modes of operation are possible Parallel Load Shift in direction QA towards QD Parallel loading is accomplished by applying the four bits of data and taking the shift load control of input low The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input During parallel loading serial data flow is inhibited Serial shifting is accomplished synchronously when the shift load control input is high Serial data for this mode is entered at the J-K inputs These inputs allow the first stage to perform as a J-K D or T-type flip flop as shown in the truth table.
